2015-12-29 17:30:45 +01:00
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{ stdenv, fetchFromGitHub, icestorm }:
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stdenv.mkDerivation rec {
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name = "arachne-pnr-${version}";
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2016-05-21 22:23:36 +02:00
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version = "2016.05.21";
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2015-12-29 17:30:45 +01:00
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src = fetchFromGitHub {
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owner = "cseed";
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repo = "arachne-pnr";
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2016-05-21 22:23:36 +02:00
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rev = "6b8336497800782f2f69572d40702b60423ec67f";
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sha256 = "11hg17f4lp8azc0ir0i473fz9c0dra82r4fn45cr3amd57v00qbf";
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2015-12-29 17:30:45 +01:00
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};
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preBuild = ''
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makeFlags="DESTDIR=$out $makeFlags"
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'';
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makeFlags = "ICEBOX=${icestorm}/share/icebox";
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meta = {
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description = "Place and route tool for FPGAs";
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longDescription = ''
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Arachne-pnr implements the place and route step of
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the hardware compilation process for FPGAs. It
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accepts as input a technology-mapped netlist in BLIF
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format, as output by the Yosys [0] synthesis suite
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for example. It currently targets the Lattice
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Semiconductor iCE40 family of FPGAs [1]. Its output
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is a textual bitstream representation for assembly by
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the IceStorm [2] icepack command.
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'';
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homepage = https://github.com/cseed/arachne-pnr;
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license = stdenv.lib.licenses.gpl2;
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maintainers = [ stdenv.lib.maintainers.shell ];
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};
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}
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