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llvm_5: fix build with gcc9
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33
pkgs/development/compilers/llvm/5/fix-gcc9.patch
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33
pkgs/development/compilers/llvm/5/fix-gcc9.patch
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@ -0,0 +1,33 @@
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diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp
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index f79cb0e6..c6279046 100644
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--- a/lib/Target/Mips/MipsFastISel.cpp
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+++ b/lib/Target/Mips/MipsFastISel.cpp
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@@ -70,6 +70,7 @@
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#include <cassert>
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#include <cstdint>
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#include <new>
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+#include <array>
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#define DEBUG_TYPE "mips-fastisel"
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@@ -1309,13 +1310,13 @@ bool MipsFastISel::fastLowerArguments() {
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return false;
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}
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- const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
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- Mips::A3};
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- const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14};
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- const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7};
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- ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin();
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- ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin();
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- ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin();
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+ std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
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+ Mips::A3}};
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+ std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
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+ std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
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+ auto NextGPR32 = GPR32ArgRegs.begin();
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+ auto NextFGR32 = FGR32ArgRegs.begin();
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+ auto NextAFGR64 = AFGR64ArgRegs.begin();
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struct AllocatedReg {
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const TargetRegisterClass *RC;
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@ -49,6 +49,13 @@ stdenv.mkDerivation ({
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name = "llvm-gcc8-type-mismatch.patch";
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sha256 = "0ga2123aclq3x9w72d0rm0az12m8c1i4r1106vh701hf4cghgbch";
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})
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./fix-gcc9.patch
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#(fetchpatch {
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# name = "llvm-fix-gcc9.patch";
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# url = "https://reviews.llvm.org/file/data/zs3ck5ryvc5n672fd2kw/PHID-FILE-byoqefzwmkd7qnlip4v2/file";
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# sha256 = "0injj1hqgrbcbihhwp2nbal88jfykad30r54f2cdcx7gws2fcy8i";
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# stripLen = 1;
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#})
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];
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postPatch = stdenv.lib.optionalString stdenv.isDarwin ''
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substituteInPlace cmake/modules/AddLLVM.cmake \
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